1. Field of the Invention
The invention relates to capacitance multiplier circuits. More particularly, the invention relates to capacitance multiplier circuits having reduced capacitor parasitics and reduced noise.
2. Description of the Related Art
A capacitance multiplier is an electronic circuit that uses a relatively small physical capacitance to approximate a relatively larger capacitance value. Often, a capacitance multiplier is a transistor configured to multiply the value of a capacitor coupled to the base of the transistor by an amount equal to the transistor's gain, also known as beta (β). In many applications, a capacitance multiplier can be used to reduce the physical size of a capacitor in a design. For example, in an integrated circuit application where the maximum size of an on-chip capacitor may be 10 picofarads (pF) or less, a 20 times (20×) multiplier will allow capacitors of 200 pF or possibly greater to be realized on the integrated circuit chip. Other cases in which a capacitance multiplier can be used to reduce the physical size of a capacitor in a design include a miniature printed circuit board (PCB) or ceramic radio frequency (RF) modules where phase locked loop (PLL) filter capacitor values and their corresponding sizes are relatively large compared to other circuitry. Another application for using capacitance multipliers to reduce the physical size of a capacitor includes relatively low frequency filters or PLL filters with a relatively narrow loop bandwidth. In these cases, it may be difficult to implement relatively high quality capacitors, which fall in the microfarad range, in a physical size that is practical.
One problem with many conventional implementations of capacitance multiplier circuits is that the capacitor parasitics may be relatively large. In particular, the series resistance of a conventional transistor-based current mirror implementation of a capacitance multiplier may be unacceptably large, particularly in many applications that require a capacitor with a relatively large capacitance. Another problem that may occur in conventional implementations of capacitance multiplier circuits is that the noise injected into the circuit by the capacitance multiplier may degrade the performance of the associated circuits. This is particularly true in PLL applications where the capacitance multiplier replaces the dominate pole capacitor in the loop filter. In these cases, the noise of the capacitance multiplier may be large enough to degrade the PLL phase noise performance. In filter applications, the noise injected by a capacitance multiplier also can be of concern since the injected noise effectively raises the noise floor of the signal. If the filter is used in a receiver or some other noise critical system, the added noise may not be acceptable.